Abstract
This paper describes a cluster structure to reduce the amount of network hardware in distributed memory parallel processors. The expected reduction in the data transfer rate as the number of nodes is reduced is avoided by raising the transfer rate of each path. Calculations for typical application programs show that clustering can reduce the hardware quantity by 40% provided that inner-cluster parallel processing efficiency is sufficiently high.
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References
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Hanawa, M., Nishimukai, T., Nishii, O., Suzuki, M., Yano, K., Hiraki, M., Shukuri, S. and Nishida, T., “On-Chip Multiple Superscalar Processors with Secondary Cache Memories”, Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1991.
Hamanaka, N., Tanaka, T. and Muramatsu, A., “Performance Evaluation of a Numerical Calculation Oriented Macro Dataflow Computer”, Dataflow Workshop, 1987 (in Japanese).
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© 1992 Springer-Verlag Berlin Heidelberg
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Hamanaka, N., Nakagoshi, J., Tanaka, T. (1992). Reducing network hardware quantity by employing multi-processor cluster structure in distributed memory parallel processors. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_393
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DOI: https://doi.org/10.1007/3-540-55895-0_393
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