Abstract
The purpose of this work is to present two novel architectures for inner product computation. The proposed architectures incorporate shift switching into the reconfigurable buses. Given two arrays of N elements, each consisting of m bits, our first architecture achieves a latency of O((logN + logM)ta + (logN)tb), using Nm2 basic shift switches and m2 adders assuming that broadcasting on a bus takes tb time and an addition takes ta time. The second architecture extends the first one by pipelining and achieves a throughput of one inner product per lime unit, while keeping the latency unchanged. Replacing large number of adders with simple shift switches, both architectures improve the state of the art by reducing the amount of hardware for the computation.
This author was supported by National Science Foundation under grant CCR-8909996
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© 1992 Springer-Verlag Berlin Heidelberg
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Lin, R., Olariu, S. (1992). Computing the inner product on reconfigurable buses with shift switching. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_413
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DOI: https://doi.org/10.1007/3-540-55895-0_413
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