Abstract
In this paper, we present a task scheduling algorithm which accounts for digit-level pipelines of on-line arithmetic units when a limited number of heterogeneous on-line arithmetic units can be connected totally with each other and the network is reconfigurable during the execution. In on-line arithmetic, an arithmetic unit can be reused after the completion of its computing process while its result is available digit by digit during the computation. Thus, a new criterion, called the maximal delay is introduced to take into account additional precedence constraints based on the on-line delay.
This work is partially supported by the PRC “Architectures Nouvelles de Machines” of the French Ministère de l'Education Nationale and the Centre National de la Recherche Scientifique.
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© 1992 Springer-Verlag Berlin Heidelberg
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Yeh, HJ. (1992). A task scheduling algorithm for the parallel expression evaluation in a reconfigurable fully digit on-line network. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_466
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DOI: https://doi.org/10.1007/3-540-55895-0_466
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