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On the simulation of pipelining of fully digit on-line floating-point adder networks on massively parallel computers

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Book cover Parallel Processing: CONPAR 92—VAPP V (VAPP 1992, CONPAR 1992)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 634))

Abstract

This paper deals with the simulation of on-line floating-point adders networks on parallel machines. We present the first results of the simulations of pipelining at digit-level on MasPar, a massively parallel SIMD computer.

This work is part of a project called CARESSE which is partially supported by the “PRC Architectures Nouvelles de Machines” of the French Ministère de la Recherche et de la Technologie and the Centre National de la Recherche Scientifique.

On leave from Universidade Federal do Ceará/CNPq, Brazil.

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Authors and Affiliations

  1. Laboratoire de l'Informatique du Parallélisme-IMAG, Ecole Normale Supérieure de Lyon, 46 Allé d'Italie, 69364, Lyon Cedex 07, France

    Jean Duprat & Mario Fiallos Aguilar

Authors
  1. Jean Duprat
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  2. Mario Fiallos Aguilar
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Editor information

Luc Bougé Michel Cosnard Yves Robert Denis Trystram

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© 1992 Springer-Verlag Berlin Heidelberg

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Duprat, J., Aguilar, M.F. (1992). On the simulation of pipelining of fully digit on-line floating-point adder networks on massively parallel computers. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_472

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  • DOI: https://doi.org/10.1007/3-540-55895-0_472

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-55895-8

  • Online ISBN: 978-3-540-47306-0

  • eBook Packages: Springer Book Archive

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