Abstract
The near future will present large scale parallel computers, able to provide computing power of more than one TFlop per second. It is commonly agreed that these systems will be based on the model of asynchronous processors connected by a point to point network. There are a number of different network architectures presented in the past.
In this paper we present an architectural principle that combines efficiency, realizability for very large systems, and inherent reliability needed for such large parallel processing systems. The here presented Fat Mesh of Clos network principle can be scaled in many ways to fulfill the special requirements of a system design.
Two realizations of this principle are presented: One is based on static switches combined to form a fully reconfigurable system. This architecture has been realized for systems containing up to 320 processors.
The other realization uses dynamic routing switches. By combining wormhole routing with randomized and local adaptive routing this network provides large capacity and very short latency times. The efficiency of our principle is demonstrated by simulations.
Both realizations presented here are built and commercialized by Parsytec Computer.
This work was partly supported by the German Federal Department of Science and Technology (BMFT), PARAWAN project 413-5839-ITR 9007 BO and by the DFG-Forschergruppe “Effiziente Nutzung massiv paralleler Systeme”
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Monien, B., Lüling, R., Langhammer, F. (1993). A realizable efficient parallel architecture. In: Meyer, F., Monien, B., Rosenberg, A.L. (eds) Parallel Architectures and Their Efficient Use. Nixdorf 1992. Lecture Notes in Computer Science, vol 678. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56731-3_10
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DOI: https://doi.org/10.1007/3-540-56731-3_10
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