Trace-splitting for the parallel simulation of cache memory

Abstract

This paper presents two techniques enabling the trace-driven simulation of a single cache memory to be performed in parallel. They are both based on splitting the trace into sub-traces which are then separately applied to suitably modified versions of the cache simulator. The two techniques are called trace slicing and trace segmentation, after the way the trace is split, and require only large-grain parallelism. While simple, slicing leads to poor speedup due to the unbalanced distribution of references in a trace. Segmentation provides good speedup, as equations and implementation results demonstrate. For each segment, potential misses due to the unknown initial contents are recorded; the true status of these is determined at the end of the simulation. The techniques may be applicable to forms of trace-driven analysis other than cache simulation.