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Implementation of a digital modular chip for a reconfigurable artificial neural network

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Book cover PARLE '93 Parallel Architectures and Languages Europe (PARLE 1993)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 694))

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Abstract

Artificial Neural Networks (ANNs) are fast becoming an integral part of today's computing arsenal [4]. This paper discusses the issues involved in the design of a General Purpose Reconfigurable Artificial Neural Network (GPRNN). The IBM fabricated Basic Neural Unit (BNU) is used as a building block for the GPRNN. As a first step, a fully reconfigurable 2-BNU VLSI circuit is designed, implemented and tested.

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References

  1. J.E. Dayhoff, “Neural Network Architectures: An Introduction.” Van Nostrand Reinhold, New York NY, 1990.

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  2. B. Jin, S. Pakzad and A.R. Hurson, “Application of Neural Networks in Handling Large Incomplete Databases.” Proc. 1991 int. Conf. on Parallel Processing, pg. 404–408.

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  3. P. Plaskonos, S. Pakzad, B. Jin, and A.R. Hurson, “Design of a Modular Chip for a Reconfigurable Artificial Neural Network.” To be published in: Proc. Conf. on Developing and Managing Intelligent Systems Projects, March 1993.

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  4. P. Treleaven, M. Pacheo and M. Vellasco, “VLSI Architechtures for Neural Networks.”, IEEE Micro, Dec. 1989, pg. 8–27.

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  5. P.D. Wasserman and T. Schwartz, “Neural Networks, Part I.” IEEE Expert, Winter 1987, pg. 10–14.

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Arndt Bode Mike Reeve Gottfried Wolf

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© 1993 Springer-Verlag Berlin Heidelberg

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Pakzad, S., Plaskonos, P. (1993). Implementation of a digital modular chip for a reconfigurable artificial neural network. In: Bode, A., Reeve, M., Wolf, G. (eds) PARLE '93 Parallel Architectures and Languages Europe. PARLE 1993. Lecture Notes in Computer Science, vol 694. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56891-3_63

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  • DOI: https://doi.org/10.1007/3-540-56891-3_63

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56891-9

  • Online ISBN: 978-3-540-47779-2

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