Abstract
Field programmable gate arrays (FPGA) make rapid prototyping an easier task, and are useful in many applications due to their growing speed and capacity. In this paper, we present a rectification method for lookup-table type FPGA's. Instead of changing the netlist of a circuit, we only modify the functionality realized by look-up tables and keep the netlist equal so that there will be no change in the delay of the circuit. We formulate the problem using characteristic functions and present a redesign method based on Boolean relation techniques.
This work was done when the second author was at the University of Tokyo, Tokyo 113, Japan
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© 1993 Springer-Verlag Berlin Heidelberg
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Fujita, M., Kukimoto, Y. (1993). Patching method for lookup-table type FPGA's. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_30
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DOI: https://doi.org/10.1007/3-540-57091-8_30
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