Abstract
Hierarchical architectures attempt to provide the benefits of both VLIW/superscalar and MIMD machines by combining multiple VLIW or superscalar processors as parallel, asynchronous processors. An example of these architectures is the Intel Touchstone multicomputer. These machines provide the opportunity to execute a program in parallel at both the machine instruction level and the source statement level.
In this paper, we present some initial results from our research into exploiting hierarchical parallelism with the help of an optimizing compiler. The prototype compiler schedules code for a VLIW/MIMD target architecture. The compiled programs were executed on simulated MIMD and VLIW/MIMD machines. These preliminary results indicate that performing instruction level parallelization on loops that have already been parallelized at the statement level can provide an additional multiplicative speedup in the range of 3.5 to 5.3. Moreover, this factor is independent of the number of VLIW processors used.
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© 1993 Springer-Verlag Berlin Heidelberg
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Brownhill, C., Nicolau, A. (1993). A hierarchical parallelizing compiler for VLIW/MIMD machines. In: Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1992. Lecture Notes in Computer Science, vol 757. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57502-2_39
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DOI: https://doi.org/10.1007/3-540-57502-2_39
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