A 65-MHz digital chip-matched-filter for DS-spread spectrum applications

Abstract

To fulfil the demands for high speed signal processing for spread spectrum systems, VLSI ASICs are needed. They enable the design of low power consumption and small mobile terminals. The design of a chip matched filter ASIC is presented. The filter is based on the square root raised cosine function with a roll-off factor of one. To increase the maximum achievable speed of signal processing, the filter coefficients are rounded to canonic signed digit numbers. Using this technique the filter achieves clock rates up to 100 MHz. Compared to the ideal matched filter, the performance of the filter is decreased only by max. 0.3 dB.