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The instruction systolic array — Implementation of a low-cost parallel architecture as add-on board for personal computers

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Book cover High-Performance Computing and Networking (HPCN-Europe 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 797))

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Abstract

In this paper the architecture of a 1024 processor instruction systolic array is described. Besides the presentation of the concept and the architectural details of this novel type of massively parallel system the paper focusses on the problems that had to be solved during the development phase.

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References

  1. Dittrich, A., Schmeck, H.: Given's Rotation on the Instruction Systolic Array. In: Wolf, G., Legendi, T., Schendel, U. (eds.): PARCELLA '88, Mathematical Research, Bd. 48, Akademie Verlag, Berlin, 340–346 (1988)

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  2. Kunde, M. et al., The Instruction Systolic Array and its Relation to Other Models of Parallel Computers, Parallel Computing 7, 25–39, (1988)

    MathSciNet  Google Scholar 

  3. Lang, H.-W., The Instruction Systolic Array, a parallel architecture for VLSI, Integration, the VLSI Journal 4, 65–74, (1986)

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  4. Lang, H.-W., ISA and SISA, Two Variants of a General Purpose Systolic Array Architecture, 2nd Int. Conf on Supercomputing, 460–465, (1988)

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  5. Schimmler, M.: Fast Sorting on the Instruction Systolic Array, Technical Report No. 8709, Christian-Albrechts-University, Kiel, (1987)

    Google Scholar 

  6. Schmeck, H., A Comparison-Based Instruction Systolic Array, In: Robert, Y. et al. (eds): Parallel Algorithms and Architectures, North Holland (1986)

    Google Scholar 

  7. Strazdins, P.E.: Control Structures for Mesh-Connected Networks, PhD Thesis, The Australian National University, Canberra, Australia, 1990.

    Google Scholar 

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Author information

Authors and Affiliations

  1. ISATEC Soft- und Hardware GmbH, Kiel

    Manfred Schimmler, Hans-Werner Lang & Rüdiger Maaß

Authors
  1. Manfred Schimmler
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  2. Hans-Werner Lang
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  3. Rüdiger Maaß
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Editor information

Wolfgang Gentzsch Uwe Harms

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© 1994 Springer-Verlag Berlin Heidelberg

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Schimmler, M., Lang, HW., Maaß, R. (1994). The instruction systolic array — Implementation of a low-cost parallel architecture as add-on board for personal computers. In: Gentzsch, W., Harms, U. (eds) High-Performance Computing and Networking. HPCN-Europe 1994. Lecture Notes in Computer Science, vol 797. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57981-8_165

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  • DOI: https://doi.org/10.1007/3-540-57981-8_165

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57981-6

  • Online ISBN: 978-3-540-48408-0

  • eBook Packages: Springer Book Archive

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