Bypass strategy in hypercube multiprocessors by adding bus connections

Abstract

A modified hypercube architecture is proposed for greatly reducing the maximum inter-PE (processing element) distance, i.e., the diameter, and for improving communication performance with minimum hardware cost (one additional port per PE). Multiple bus connections are added while keeping the original hypercube topology and they are used as bypass routes. This is achieved by partitioning all PEs of the hypercube into subsets whose PEs are far from each other and by connecting all PEs in each subset to a bus. These subsets are basically formed by partitioning all the PE addresses using a perfect code, for example a Hamming code, and its cosets. In basic structure suitable for small hypercubes, the diameter is reduced to two, that is, one on a bus plus one on a link. In the generalized structure suitable for large hypercubes which can keep the number of PEs connected to a bus small, the diameter is reduced to less than about one-third of those of the regular hypercube with more bypass routes.