Abstract
In this paper we gave some methods how the complexity of a design description can be quantified and what is the largest complexity that can be implemented on a given type of XILINX chip using the standard XACT design system. These methods can be used to partition a large design task, given by either a circuit schematic or an algorithm, to smaller ones which can be implemented in FPGA chips.
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References
P.Szolgay,” On algorithms in the parallel design of logic and layout of circuits with functional blocks”, Int. J. of Circuit Theory and Applications, Vol.20, pp.411–429, (1992.)
The Programmable Gate Array Data Book 1992, Xilinx, San Jose, California
M.H.Halstead, Elements of Software Science, Elsevier North-Holland, Amsterdam, 1977.
Special Section on Field Programmable Gate Arrays (ed. A. El Gammal), Proc. of the IEEE Vol. 81, No. 7, July 1993 pp. 1011–1083
A.Katona and P.Szolgay, “Limits of XILINX based control logic implementations”, IT-2-1993, University of Veszprém
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© 1994 Springer-Verlag Berlin Heidelberg
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Katona, A., Szolgay, P. (1994). On some limits of XILINX based control logic implementations. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_102
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DOI: https://doi.org/10.1007/3-540-58419-6_102
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