Skip to main content
SpringerLink
Log in
Book cover

International Workshop on Field Programmable Logic and Applications

FPL 1994: Field-Programmable Logic Architectures, Synthesis and Applications pp 332–334Cite as

Implementation and performance evaluation of an image pre-processing chain on FPGA

  • Conference paper
  • First Online:

  • 303 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

Abstract

An efficient implementation of a low level image processing algorithm on FPGA requires to consider the particularities of the device architecture in the design of the application architecture and different optimization levels. The proposed evaluation method allows to study the feasibility on Xilinx circuits to implement low level image processing tasks at video rate.

This is a preview of subscription content, log in via an institution.

Bibliography

  1. M. ALVES DE BARROS, M. AKIL. “Circuits Reconfigurables et Traitement Bas Niveau d'Images en Temps Réel”. Ann. 14ème GRETSI, Juan les Pins, France, Sept. 1993.

    Google Scholar 

  2. The XC4000 Programmable Gate Array Data Book, Xilinx, San Jose, USA, 1992.

    Google Scholar 

  3. P. M. NARENDA “ A separable median filter for image noise smoothing”, In: Digital Image Processing and Analysis. Vol 1, IEEE Computer Society, 1985, 450–459.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Groupe ESIEE, Laboratoire IAAI, Cité Descartes, 2, Bd. Blaise Pascal, BP 99, 93162, Noisy Le Grand Cedex, France

    Mohamed Akil & Marcelo Alves De Barros

Authors
  1. Mohamed Akil
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Marcelo Alves De Barros
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Reiner W. Hartenstein Michal Z. Servít

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Akil, M., De Barros, M.A. (1994). Implementation and performance evaluation of an image pre-processing chain on FPGA. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_115

Download citation

  • DOI: https://doi.org/10.1007/3-540-58419-6_115

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation