Abstract
This paper deals with the design of a Built-in Self Test (BIST) environment for the Programmable Logic Arrays that minimizes the aliasing probability. The signature testability condition is developed that prove criteria to compare the BIST environment aliasing. An important feature of the developed approach is that the criteria proved by signature testability allows to design both pseudo-random test pattern generator (PRPG) and signature analyzer (SA).
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References
Pradhan D.K. and Gupta S.K. ”A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression”, IEEE Trans. on Computers, vol. 40, N 6, June 1991, pp. 743–763.
Nagvajara P., Karpovsky M.G., ”Coset Error Detection in BIST Design”, IEEE VLSI Test Symposium 1992, pp. 79–83.
Yarmolik V.N., Kalosha E.P., ”Signature-Testable LSSD-Circuits”, Avtomatika i Vychislitelnaya Technika, 1990, N 1, pp. 94–95.
MacWilliams F.J. and Sloane N.J.A., ”The Theory of Error-Correcting Codes”, NewYork: North-Holland, 1977.
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© 1994 Springer-Verlag Berlin Heidelberg
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Kalosha, E.P., Yarmolik, V.N., Karpovsky, M.G. (1994). Signature testability of PLA. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_116
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DOI: https://doi.org/10.1007/3-540-58419-6_116
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