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A high-speed rotation processor

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Field-Programmable Logic Architectures, Synthesis and Applications (FPL 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

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Abstract

We present a high-speed rotation processor for rotating digital images based on the backrotation algorithm. The design is part of our research project on real time volume visualization architectures. The processor is implemented on an Actel FPGA and the solution is compared to a Xilinx implementation. Performance measurements show a throughput of more than 360 images per second with 2562 pixels per image. Each pixel is represented with 12 bit data.

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References

  1. Joel H. Dedrick: Transforming Digital Images in Real Time. The Electronic Design Magazine, 27–30, August 1987

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  2. Jan Lichtermann, Gangolf Millelhäußer: Eine Hardwarcarchitektur zur Echtzeitvisualisierung von Volumendaten durch ‘Direct Volume Rendering', GI Workshop Visualisierungstechniken, Stuttgart, June 1991 (in German)

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  3. Jan Lichtermann, Günter Neustädter: A High-Speed Rotation Processor for the PIV2-Architecture, SFB 124 Report, University of Kaiserslautern, Germany, 1994

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Reiner W. Hartenstein Michal Z. Servít

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© 1994 Springer-Verlag Berlin Heidelberg

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Lichtermann, J., Neustädter, G. (1994). A high-speed rotation processor. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_78

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  • DOI: https://doi.org/10.1007/3-540-58419-6_78

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

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