Abstract
Fractal image compression appears to be a good candidate for implementation with a reprogrammable processor. It is computationally intensive, slow on existing technology, and employs a few basic, welldefined functions that are clear candidates for hardware implementation. We discuss our implementation of a reconfigurable processor for fractal image compression, used to evaluate the utility of different compression methods faster than a software-only approach.
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References
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© 1994 Springer-Verlag Berlin Heidelberg
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Fagin, B., Chintrakulchai, P. (1994). A reprogrammable processor for fractal image compression. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_80
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DOI: https://doi.org/10.1007/3-540-58419-6_80
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Online ISBN: 978-3-540-48783-8
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