Skip to main content

A superscalar and reconfigurable processor

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

Abstract

Spyder is a processor architecture with three concurrent, reconfigurable execution units implemented by FPGAs. This paper presents the hardware evolution of the Spyder processor and its evolving software development environment.

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. David A. Patterson and John L. Hennessy, Computer Organization & Design, The Hardware/Software Interface, Morgan Kaufmann Publishers, San Mateo, 1994.

    Google Scholar 

  2. Christian Iseli and Eduardo Sanchez, “Spyder: A reconfigurable VLIW processor using FPGAs”, in IEEE Workshop on FPGAs for Custom Computing Machines, Napa, April 1993.

    Google Scholar 

  3. B. Ramakrishna Rau and Joseph A. Fisher, “Instruction-level parallelism: History, overview, and perspectives”, in Instruction-Level Parallelism, B. Ramakrishna Rau and Joseph A. Fisher, Eds., pp. 9–50. Kluwer Academic Publishers, Boston, 1993.

    Google Scholar 

  4. Sun Microsystems, The SPARC Architecture Manual, Sun Microsystems, Inc, Mountain View, 1987.

    Google Scholar 

  5. Xilinx, The Programmable Logic Data Book, Xilinx, San Jose, 1993.

    Google Scholar 

  6. Motorola, Phoenix, Arizona, PowerPC 601 RISC Microprocessor User's Manual, 1993.

    Google Scholar 

  7. Kendall Preston Jr., “The abingdon cross benchmark survey”, IEEE Computer, vol. 22, no. 7, pp. 9–18, July 1989.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Reiner W. Hartenstein Michal Z. Servít

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Iseli, C., Sanchez, E. (1994). A superscalar and reconfigurable processor. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_87

Download citation

  • DOI: https://doi.org/10.1007/3-540-58419-6_87

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics