Meaningful benchmarks for logic optimization of table-lookup FPGAs

Abstract

This paper discusses benchmarks for optimization to table-lookup FPGAs. We discuss a scientific method for systematically generating a set of benchmarks for measuring the effectiveness of a synthesis tool/algorithm for a particular FPGA architecture. The benchmarks have the useful properties of being generated easily, having an a priori, known best result, covering all the possible configurations of a lookup table, and yielding a simple metric. This metric can be used to compare different synthesis tools/algorithms for their efficiency in mapping to a given FPGA architecture. This is in contrast to the ad hoc sets of benchmarks, for which it is difficult to compare results of different optimization tools/algorithms.