Abstract
ARTL (Algorithmic Register Transfer Language) is a language used to describe and specify synchronous hardware at the algorithmic and register-transfer levels. Its syntax and natural semantics are formalized in higher-order logic using HOL. An ARTL simulation engine (abstract machine) and compiler are described and verified within HOL. The machine and compiler for ARTL is fully implemented. Also, we present the principles of ARTL synthesis using to standard cells and field programmable gate arrays (FPGAs).
Supported by NY State Center for Advanced Technology at Syracuse University.
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Lu, JY., Chin, SK. (1994). Generating designs using an Algorithmic Register Transfer Language with formal semantics. In: Melham, T.F., Camilleri, J. (eds) Higher Order Logic Theorem Proving and Its Applications. HUG 1994. Lecture Notes in Computer Science, vol 859. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58450-1_51
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DOI: https://doi.org/10.1007/3-540-58450-1_51
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