Further pipelining and multithreading to improve RISC processor speed. A proposed architecture and simulation results

Abstract

This paper presents a new pipeline architecture which should improve both the number of Cycles Per Instruction (CPI) and the cycle width. The pipe stage critical path, imposed by the 64 bits integer unit, has been cut in half by data slicing and pipelining the Arithmetic and Logic Unit (ALU). Moreover, because this proposed pipeline stages division should impose a very long latency for CPU external accesses, a multithreading structure has been included. Up to four threads may be simultaneously run with a no delay context switch. Thus, multithreading is mainly used as a latency hiding technique for external accesses and internal dependencies. In order to estimate the real benefit of the construct, a simulator has been built. Simulation results show the impact of pipeline improvements without multithreading (between 24% and 32% according to cache size) and with it (from 56% to 65% with four threads and same caches).