Abstract
It is shown how a significant subset of VHDL has been deep embedded in HOL along with the four abstraction types of hardware: behavioral, structural, data, temporal.
First, a method for simplifying deep embedding of languages in HOL is presented: derivation trees as a representation of a syntax in HOL are automatically generated out of a given context-free grammar; a formal, functional compiler as a representation of the semantics in HOL is automatically generated out of a given set of attributation and translation rules.
Second, the formal base for a VHDL semantics in HOL consists of: a flowgraph model as a special form of a state transition system for describing behavioral VHDL, a hierarchical combination of state transition systems for describing structural VHDL and a formalization of scalar datatypes of VHDL.
Third, a VHDL semantics is presented, which enables temporal abstraction by preserving hierarchy.
This work was financed by the German research society under contract SFB 358.
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Reetz, R. (1995). Deep embedding VHDL. In: Thomas Schubert, E., Windley, P.J., Alves-Foss, J. (eds) Higher Order Logic Theorem Proving and Its Applications. TPHOLs 1995. Lecture Notes in Computer Science, vol 971. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60275-5_71
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DOI: https://doi.org/10.1007/3-540-60275-5_71
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