An automatic technique for realising user interaction processing in PLD based systems

Abstract

This paper has described how a shift-reduce parser can be implemented in hardware. Of more significance is the way in which the architecture has been tailored to the specific logical structures of fpgas. The paper then describes how the hardware can be constructed automatically by analysing the output of the compiler-compiler. Although the example cited in the paper very simple the method has been used to develop sophisticated user interfaces for domestic electronic equipment. Whilst the Xilinx fpga is used in this paper studies are continuing to examine other types. With the current implementation this design takes approximately 90 CLBs to realise, it is expected that finer grain fpgas could offer some interesting advantages.