Abstract
Many DSP functions can be implemented as arrays of simple Processing Elements (PEs) connected to their nearest neighbours in a regular manner. Field Programmable Gate Arrays consist of an array of user-configurable logic blocks and a matrix of user configurable interconnection between the logic blocks. Thus FPGAs are prime candidates for implementing regular arrays. In this paper we present FPGA Regular Array Description Language (FRADL) which will map the regular array into a FPGA.
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Marnane, W.P., Jordan, C.N., O'Reilly, F.J. (1995). Compiling regular arrays onto FPGAs. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_111
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DOI: https://doi.org/10.1007/3-540-60294-1_111
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