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An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system

  • Arithmetic and Signal Processing
  • Conference paper
  • First Online:
Field-Programmable Logic and Applications (FPL 1995)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 975))

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Abstract

This paper describes the development of a prototype 64-tap multiplierless FIR filter based on the Logarithmic Number System (LNS). The circuit has been implemented and tested using a single Xilinx X64C64 device with external coefficient memory, data memory, ADC and DAC. The filter samples at 14KHz and runs at a rate of 895KHz (64 × 14KHz). This architecture is suitable for implementation using custom VLSI and can provide a compact, low-power solution to a number of simple filtering problems. It can also be expanded or cascaded to produce higher order filters.

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References

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Author information

Authors and Affiliations

  1. University of Kent at Canterbury, CT2 7NT, Canterbury, Kent

    Pter Lee

Authors
  1. Pter Lee
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Editor information

Will Moore Wayne Luk

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© 1995 Springer-Verlag Berlin Heidelberg

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Lee, P. (1995). An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_124

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  • DOI: https://doi.org/10.1007/3-540-60294-1_124

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-60294-1

  • Online ISBN: 978-3-540-44786-3

  • eBook Packages: Springer Book Archive

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