Abstract
The implementation of finite impulse response (FIR) digital filters using pipelined bit-serial arithmetic and canonic signed digit (CSD) coefficient coding can be an effective use of hardware resources. However, the necessary time alignment of all data and control signals can be a tedious process. A methodology for implementing FIR filters using pipelined bit-serial arithmetic and field programmable gate arrays (FPGAs) is described.
This work was supported in part by funding from the National Sciences and Engineering Research Council of Canada and Micronet, A Canadian Network of Centres of Excellence.
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© 1995 Springer-Verlag Berlin Heidelberg
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Turner, L.E., Graumann, P.J.W., Gibb, S.G. (1995). Bit-serial FIR filters with CSD coefficients for FPGAs. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_125
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DOI: https://doi.org/10.1007/3-540-60294-1_125
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