Abstract
With the introduction of Splash, Splash 2, PAM, and other reconfigurable computers, a wide variety of algorithms can now be feasibly constructed in hardware. In this paper, we describe the Splash 2 Parallel Genetic Algorithm (SPGA), which is a parallel genetic algorithm for optimizing symmetric traveling salesman problems (TSPs) using Splash 2. Each processor in SPGA consists of four Field Programmable Gate Arrays (FPGAs) and associated memories and was found to perform 6.8 to 10.6 times the speed of equivalent software on a state-of-the-art workstation. Multiple processor SPGA systems, which use up to eight processors, find good TSP solutions much more quickly than single processor and software-based implementations of the genetic algorithm. The four-processor island-parallel SPGA implementation out performed all other SPGA configurations tested. We conclude noting that the described parallel genetic algorithm appears to be a good match for reconfigurable computing machines and that Splash 2's various interconnect resources and support for linear systolic and MIMD computing models was important for the implementation of SPGA.
This work was supported by ARPA/CSTO under contract number DABT63-94-C-0085 under a subcontract to National Semiconductor
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© 1995 Springer-Verlag Berlin Heidelberg
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Graham, P., Nelson, B. (1995). A hardware genetic algorithm for the traveling salesman problem on Splash 2. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_129
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DOI: https://doi.org/10.1007/3-540-60294-1_129
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