Abstract
Current trends in system design are pointing to using more and more processing units and storage units in a single system. In order to generate programs for these types of distributed memory machines, the challenge is to coordinate and schedule multiple functional units to perform computations efficiently.
In this paper, we describe how our compiler can automate the process and generate good parallel programs from sequential programs. We show how to turn the straight-line code into a task graph which exhibits maximum parallelism possible. Then we give an algorithm for assigning computation to processors to minimize communication cost. Finally, we give an algorithm to allocate registers across processors using an interference graph.
Supported in part by the Advanced Research Projects Agency of the Department of Defense under ONR Contract N00014-92-J-1989, by ONR Contract N00014-92-J-1839, United States-Israel Binational Science Foundation Grant 92-00234 and in part by the U.S. Army Research Office through the Mathematical Science Institute of Cornell University.
Supported by a Fannie and John Hertz Foundation Fellowship.
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© 1995 Springer-Verlag Berlin Heidelberg
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Hao, B., Pearson, D. (1995). Instruction scheduling and global register allocation for SIMD multiprocessors. In: Ferreira, A., Rolim, J. (eds) Parallel Algorithms for Irregularly Structured Problems. IRREGULAR 1995. Lecture Notes in Computer Science, vol 980. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60321-2_6
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DOI: https://doi.org/10.1007/3-540-60321-2_6
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