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Annual Symposium on Theoretical Aspects of Computer Science

STACS 1996: STACS 96 pp 193–204Cite as

On word-level parallelism in fault-tolerant computing

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1046))

Abstract

In this paper we present several simulations of operational PRAM on PRAM with memory or processor faults. Their common property is that they rely on the ability of performing standard boolean or arithmetic operations on words consisting of many bits.

The author would like to thank to Bogdan Chlebus, Suresh Venkatasubramanian and the anonymous referees, who helped to improve the readability of this paper.

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Author information

Authors and Affiliations

  1. Computer Science Department, Stanford University, USA

    Piotr Indyk

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  1. Piotr Indyk
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Claude Puech Rüdiger Reischuk

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© 1996 Springer-Verlag Berlin Heidelberg

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Indyk, P. (1996). On word-level parallelism in fault-tolerant computing. In: Puech, C., Reischuk, R. (eds) STACS 96. STACS 1996. Lecture Notes in Computer Science, vol 1046. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60922-9_17

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  • DOI: https://doi.org/10.1007/3-540-60922-9_17

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-60922-3

  • Online ISBN: 978-3-540-49723-3

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