Abstract
An analog neural network with four neurons and 16 synapses, fabricated in a 1.2 μm n-well single-polysilicon, double-metal process, is presented. The circuit solutions adopted, for on-chip learning and weight storage, particularly simple and silicon area-efficient, are capable of solving the main problems to the implementation of analog neural networks.
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© 1996 Springer-Verlag Berlin Heidelberg
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Conti, M., Guaitini, G., Turchetti, C. (1996). An analog CMOS neural network with on-chip learning and multilevel weight storage. In: von der Malsburg, C., von Seelen, W., Vorbrüggen, J.C., Sendhoff, B. (eds) Artificial Neural Networks — ICANN 96. ICANN 1996. Lecture Notes in Computer Science, vol 1112. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61510-5_128
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DOI: https://doi.org/10.1007/3-540-61510-5_128
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