Abstract
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1μA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.
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© 1996 Springer-Verlag Berlin Heidelberg
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Demosthenous, A., Taylor, J., Smedley, S. (1996). A high-speed scalable CMOS current-mode Winner-Take-All network. In: von der Malsburg, C., von Seelen, W., Vorbrüggen, J.C., Sendhoff, B. (eds) Artificial Neural Networks — ICANN 96. ICANN 1996. Lecture Notes in Computer Science, vol 1112. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61510-5_65
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DOI: https://doi.org/10.1007/3-540-61510-5_65
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