Abstract
Artificial neural networks achieve fast parallel processing via massively parallel non-linear computational elements. Most neural network models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices allow the implementation of neural networks with in-circuit structure adaptation. This paper describes an FPGA implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a neural network that dynamically changes its size. Since initial experiments indicated a good performance on pattern clustering tasks, we have applied our dynamic-structure FAST neural network to an image segmentation and recognition problem.
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References
A. Alpaydin: Neural Models of Incremental Supervised and Unsupervised Learning Thesis 863, Swiss Federal Institute of Technology, Lausanne, 1990.
G. Carpenter and S. Grossberg: ”Self-Organization of stable category recognition codes for analog pattern” Applied Optics Vol 26, 1987
D. Benitez Diaz and J. Garcma Quesada: “Learning Algorithm with Gaussian Membership Function for Fuzzy RBF Neural Networks” From Natural to Artificial Neural Computation Springer Verlag 1995.
E. Fiesler: ”Comparative Bibliography of Ontogenic Neural Networks” Proceedings of the International Conference on Artificial Neural Networks (ICANN'94)
B.Fritzke: ”Growing Cell Structures — a self-organizing network in k dimensions” Artificial Neural Networks 2 1992
“I-CUBE. The FPID Family Data Sheet” I-CUBE,Inc May, 1994
Y. Ohta: “Knowledge-Based Interpretation of Outdoor Natural Color Scenes” Pitman Advanced Publishing Program 1995
W. Pries and A. Thanailakis and H. C. Card: “Group Properties of Cellular Automata and VLSI Applications” IEEE Transactions on Computers December, 1986
S.M. Trimberger: Field-Programmable Gate Array Technology Kluwer Academic Publishers, Boston, 1994.
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© 1996 Springer-Verlag Berlin Heidelberg
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Pérez-Uribe, A., Sanchez, E. (1996). FPGA implementation of an adaptable-size neural network. In: von der Malsburg, C., von Seelen, W., Vorbrüggen, J.C., Sendhoff, B. (eds) Artificial Neural Networks — ICANN 96. ICANN 1996. Lecture Notes in Computer Science, vol 1112. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61510-5_67
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DOI: https://doi.org/10.1007/3-540-61510-5_67
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