Skip to main content

Partial orders and verification of real-time systems

  • Selected Presentations
  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1135))

Abstract

We show in this paper how the verification method of timed graphs ([1], [6]) can be substantially improved by the use of a partialorder technique. In [5] and [4] is presented an efficient model-checking algorithm for concurrent systems that avoids most of the state explosion due to the modeling of concurrency by interleaving. We adapt this work to timed graphs, by defining a dependency relation on transitions and an equivalence on executions, taking into account quantitative aspects of time. We then propose a selective search algorithm that computes a reduced accessibility graph, in the framework of deadlock detection.

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. R. Alur and D. Dill. A theory of timed automata. Theoretical Computer Science, 126(2):183–235, April 1994.

    Google Scholar 

  2. E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finite state concurrent systems using temporal logic specifications: a practical approach. ACM83, pages 117–126, 1983.

    Google Scholar 

  3. D. Dill. Timing assumptions and verifications of finite-state concurrent systems. In J. Sifakis, editor, CAV89: Automatic Verification Methods for Finite-state Systems, pages 197–212. Springer-Verlag, 1989.

    Google Scholar 

  4. P. Godefroid. Partial-Order Methods for the Verification of Concurrent Systems. PhD thesis, Université de Liège, 1995.

    Google Scholar 

  5. P. Godefroid and P. Wolper. Using partial orders for the efficient verification of deadlock freedom and safety properties. Formal methods in system design, pages 149–164, 1993.

    Google Scholar 

  6. T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine. Symbolic model checking for real-time systems. Information and computation, pages 193–244, 1994.

    Google Scholar 

  7. A. Mazurkiewicz. Basic notions of trace theory. LNCS 354: Linear time, branching time and partial order in logics and models for concurrency, pages 285–363, May/June 1988.

    Google Scholar 

  8. A. Olivero. Modélisation et analyse des systèmes temporisés et hybrides. PhD thesis, Institut National Polytechnique de Grenoble, September 1994.

    Google Scholar 

  9. T. Yoneda, A. Shibayama, B-H. Schlingloff, and E. Clarke. Efficient verification of parallel real-time systems. In LNCS 697: CAV'93, pages 321–332, 1993.

    Google Scholar 

  10. S. Yovine. Méthodes et outils pour la vérification symbolique de systèmes temporisés. PhD thesis, Institut National Polytechnique de Grenoble, 1993.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Bengt Jonsson Joachim Parrow

Rights and permissions

Reprints and permissions

Copyright information

© 1996 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Pagani, F. (1996). Partial orders and verification of real-time systems. In: Jonsson, B., Parrow, J. (eds) Formal Techniques in Real-Time and Fault-Tolerant Systems. FTRTFT 1996. Lecture Notes in Computer Science, vol 1135. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61648-9_49

Download citation

  • DOI: https://doi.org/10.1007/3-540-61648-9_49

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61648-1

  • Online ISBN: 978-3-540-70653-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics