Key issues for user acceptance of FPGA design tools

Abstract

There is hardly a field in the EDA community where latest research activities and real use of tools is so divergent as in the case of synthesis for FPGAs. Latest research work for FPGA synthesis and also available tools are quickly proceeding towards the third level of synthesis, behavioral synthesis. On the other hand, the majority of FPGA designs is still done today using schematic entry. This paper first enumerates some potential reasons for the reluctance of FPGA designers to use synthesis tools. After that, some important prerequisites are discussed which the author considers absolutely necessary to improve the acceptance of synthesis tools amongst FPGA designers.