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Architectural synthesis techniques for dynamically reconfigurable logic

  • Reconfiguration Aspects
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Field-Programmable Logic Smart Applications, New Paradigms and Compilers (FPL 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1142))

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Abstract

In this paper, we address the architectural synthesis for dynamically reconfigurable logic (DRL). We focus on a scheduling problem, which has a mandatory impact on quality of the final design. An efficient heuristic algorithm is presented, which searches for an optimal solution for DRL scheduling. The results from our experiments are demonstrated on an elliptic wave filter high-level synthesis benchmark. We also discuss register allocation and resource sharing problems for DRL architectural synthesis.

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References

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Author information

Authors and Affiliations

  1. Microelectronic Systems Research Group Department of Electronics, Bournemouth University, Talbot Campus, Fern Barrow, BH12 5BB, Poole, Dorset, UK

    Milan Vasilko & Djamel Ait-Boudaoud

Authors
  1. Milan Vasilko
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  2. Djamel Ait-Boudaoud
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Editor information

Reiner W. Hartenstein Manfred Glesner

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© 1996 Springer-Verlag Berlin Heidelberg

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Vasilko, M., Ait-Boudaoud, D. (1996). Architectural synthesis techniques for dynamically reconfigurable logic. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_31

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  • DOI: https://doi.org/10.1007/3-540-61730-2_31

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61730-3

  • Online ISBN: 978-3-540-70670-0

  • eBook Packages: Springer Book Archive

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