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International Workshop on Field Programmable Logic and Applications

FPL 1996: Field-Programmable Logic Smart Applications, New Paradigms and Compilers pp 317–326Cite as

Architectural strategies for implementing an image processing algorithm on XC6000 FPGA

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1142))

Abstract

The adoption of FPGA technology for custom computing and other applications will depend greatly on how efficiently architectures may be implemented. In this paper we investigate architectural strategies for implementing a typical image processing algorithm, in this case, Laplacian convolution, on the Xilinx XC6000 series technology. Three approaches are illustrated and the resulting designs are presented. Discussion for extending this work to operate with a high level design tool currently under development, is also given.

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References

  1. W. Luk, D. Ferguson, I. Page, “Structured Hardware Compilation of Parallel Programs”, More FPGA's, Abingdon EE&CS Books 1993, pp 213.

    Google Scholar 

  2. N.B. Bhat, “A New Library-Based Mapper for LUT FPGA's”, More FPGA's, Abingdon EE&CS Books 1993, pp 138.

    Google Scholar 

  3. R. Woods, D. Crookes, W. Cochrane, A. Mitchell “Image Co-Processor Based on Reconfigurable Hardware”, Irish DSP and Control Colloquium, July 7–8th, 1994, pp 341–350

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  4. XC6200 FPGA Family Data Sheet, Xilinx Inc. 1996

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  5. M. Alexander, J. Cohoon, J. Ganley, G. Robins “Performance-Oriented Placement and Routing For Field-Programmable Gate Arrays” Euro-DAC.'95 Proceedings. IEEE Computer Society Press, pp 80.

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  6. D.W. Trainor, R.F. Woods, J.V. McCanny, “Architectural Synthesis of an Image Processing Algorithm Using Iris”, Proceedings of the IEEE Workshop on VLSI Signal Processing, Osaka, Japan, Oct. 16–18 1995, pp. 167–176.

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Authors and Affiliations

  1. The Department of Electrical and Electronic Engineering, The Queen's University of Belfast, BT9 5AH, Belfast, Northern Ireland

    J. P. Heron & R. F. Woods

Authors
  1. J. P. Heron
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  2. R. F. Woods
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Editor information

Reiner W. Hartenstein Manfred Glesner

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© 1996 Springer-Verlag Berlin Heidelberg

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Heron, J.P., Woods, R.F. (1996). Architectural strategies for implementing an image processing algorithm on XC6000 FPGA. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_34

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  • DOI: https://doi.org/10.1007/3-540-61730-2_34

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61730-3

  • Online ISBN: 978-3-540-70670-0

  • eBook Packages: Springer Book Archive

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