FPGA design migration: Some remarks

Abstract

Problems facing in design migration from FPGA to standard cells design approach are discussed. Standard cell implementation of a parallel multiplier with bit-sequential input and output, using FPGA design as a prototype is considered. It is shown that careful redesign is required, because of incompatibility of the cell libraries. Also the FPGA design complexities don't present any relation to design complexity estimation in semi-custom integrated circuits, because equivalent gate count, commonly used by manufactures, is not an appropriated measure parameter in programmable logic devices. Applying logic circuit optimization as a manner to improve design performances in terms of speed and die size is also outlined.