Abstract
In this paper we present an universal module generator for hierarchical carry lookahead adders of any word length which is suitable for most SRAM-based FPGA architectures. We introduce a generic model of SRAM-based FPGAs taking different configurations of the logic blocks into account. Considering the logical structure of CLA adders we efficiently perform technology mapping including an adaptive structure generation process as well as signal flow driven placement and partitioning which is necessary if the macro exceeds the limitations given by the FPGA's pin or CLB count.
Preview
Unable to display preview. Download preview PDF.
References
Xilinx — X-BLOX — User Guide. 1994
Synopsys — DesignWare Components Databook, Version 3.1b, 1994
S. Riedel, H.-J. Brand, D. Müller: “Entwicklung und Implementierung eines Algorithmus zur parametergesteuerten Generierung von Zählernetzlisten”, 2. GI/ITG Workshop “Anwenderprogrammierbare Schaltungen”, Karlsruhe, pp. 93–99, 1995
A. R. Naseer, M. Balakrishnan, A. Kumar: “An Efficient Technique for Mapping RTL Structures onto FPGAs”, Proc. 4th Int. Workshop on FPGAs, FPL'94, pp. 99–110, 1994
Xilinx — The Programmable Gate Array Data Book, 1994
F. Dresig, O. Rettig, U. Baitinger: “Logic Synthesis for Universal Logic Cells”, in “FPGAs”, W. R. Moore & Luk (eds.), Abingdon EE&CS Books, pp. 179–190 1991
K. Hwang: “Computer Arithmetic — Principles, Architecture, and Design”, John Wiley & Sons, 1979
M. J. Alexander, J. P. Cohoon, J. L. Ganley, G. Robins: “Performance-Oriented Placement and Routing for Field-Programmable Gate Arrays”, IEEE Proc. of European Design Automation Conf., Brighton, pp. 80–85, 1995
K. Zhu, D. F. Wong: “Clock Skew Minimization During FPGA Placement”, Proc. of ACM/IEEE Design Automation Conf.,San Diego, pp. 232–237, 1994
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Stohmann, J., Barke, E. (1996). An universal CLA adder generator for SRAM-based FPGAs. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_5
Download citation
DOI: https://doi.org/10.1007/3-540-61730-2_5
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61730-3
Online ISBN: 978-3-540-70670-0
eBook Packages: Springer Book Archive