Abstract
Yield enhancement through the acceptance of partially good chips is a well-known technique [1–3]. In this paper we derive a yield model for single-chip VLSI processors with a partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area and various manufacturing process parameters as defect densities and the fault clustering parameter.
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© 1996 Springer-Verlag Berlin Heidelberg
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Nikolos, D., Vergos, H.T. (1996). On the yield of VLSI processors with on-chip CPU cache. In: Hlawiczka, A., Silva, J.G., Simoncini, L. (eds) Dependable Computing — EDCC-2. EDCC 1996. Lecture Notes in Computer Science, vol 1150. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61772-8_40
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DOI: https://doi.org/10.1007/3-540-61772-8_40
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