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ATLAS I: A single-chip ATM switch for NOWs

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1199))

Abstract

Although ATM (Asynchronous Transfer Mode), is a widely accepted standard for WANs (Wide Area Networks), it has not yet been widely embraced by the NOW community, because (i) most current ATM switches (and interfaces) have high latency, and and (ii) they drop cells when (even short-term) congestion happens. In this paper, we present ATLAS I, a single-chip ATM switch with 20 Gbits/sec aggregate I/O throughput, that was designed to address the above concerns. ATLAS I provides sub-microsecond cut-through latency, and (optional) back-pressure (credit-based) flow control which never drops ATM cells. The architecture of ATLAS I has been fully specified and the design of the chip is well under progress. ATLAS I will be fabricated by SGS Thomson, Crolles, France, in 0.5 μm CMOS technology.

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References

  1. T.E. Anderson, D.E. Culler, and D.A. Patterson. A Case for NOW (Networks of Workstations). IEEE Micro, 15(1):54–64, February 1995.

    Google Scholar 

  2. N.J. Boden, D. Cohen, and W.-K. Su. Myrinet: A Gigabit-per-Second Local Area Network. IEEE Micro, 15(1):29, February 1995.

    Google Scholar 

  3. S. Borkar and e.a. Supporting Systolic and Memory Communication in iWarp. In Proc. 17-th International Symposium on Comp. Arch., pages 70–81, 1990.

    Google Scholar 

  4. G. Varghese C. Ozveren, R. Simcoe. Reliable and Efficient Hop-by-Hop Flow Control. IEEE Journal on Selected Areas in Communications, 13(4):642–650, May 1995.

    Google Scholar 

  5. J. Carbonaro and F. Verhoorn. Cavallino: The TeraFlops Router and NIC. In Proceedings of the Hot Interconnects IV Symposium, pages 157–160, 1996.

    Google Scholar 

  6. C. Courcoubetis, G. Fouskas, and R. Weber. An On-Line Estimation Procedure for Cell-Loss Probabilities in ATM links. In Proceedings of the 3rd IFIP Workshop on Performance Modelling and Evaluation of ATM Networks, July 1995.

    Google Scholar 

  7. D. Culler, J.P. Singh, and A. Gupta. Parallel Computer Δrchitecture. Morgan Kaufmann, 1996.

    Google Scholar 

  8. M.D. Dahlin. Serverless Network File Systems. PhD thesis, University of California at Berkeley, 1996.

    Google Scholar 

  9. W. J. Dally and C. L. Seitz. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. IEEE Transactions on Computers, C-36:547–53, May 1987.

    Google Scholar 

  10. W.J. Dally. Virtual-Channel Flow Control. In Proceedings of the 17th Int. Symposium on Computer Architecture, pages 60–68, May 1990.

    Google Scholar 

  11. T. von Eicken, D. E. Culler, S. C. Goldstein, and K. E. Schauser. Active Messages: A Mechanism for Integrated Communication and Computation. In Proc. 19-th International Symposium on Comp. Arch., pages 256–266, Gold Coast, Australia, May 1992.

    Google Scholar 

  12. M. Galles. The SGI SPIDER Chip. In Proceedings of the Hot Interconnects IV Symposium, pages 141–146, 1996.

    Google Scholar 

  13. M. Gerla and L. Kleinrock. Flow Control: A Comparative Survey. IEEE Trans. on Communications, 28(4):553–574, 1980.

    Google Scholar 

  14. A. Giessler and e.a. Free Buffer Allocation — An Investigation by Simulation. Comput. Networks, 2:191–208, 1978.

    Google Scholar 

  15. R. Gillett. Memory Channel Network for PCI. IEEE Micro, 16(1):12, February 1996.

    Google Scholar 

  16. D. B. Gustavson. The Scalable Coherent Interface and Related Standards Projects. IEEE Micro, 12(2):10–22, February 1992.

    Google Scholar 

  17. E. Hahne and R. Gallager. Round Robin Scheduling for Fair Flow Control in Data Communication Networks. In Proc. IEEE Int. Conf. on Commun., pages 103–107, 1986.

    Google Scholar 

  18. V. Jacobson. Congestion Avoidance and Control. In Proceedings of the ACM SIGCOMM '88 Conference, pages 314–329, 1988.

    Google Scholar 

  19. M. Karol, M. Hluchyj, and S. Morgan. Input versus Output Queueing on a Space-Division Packet Switch. IEEE Trans. on Communications, COM-35(12):1347–1356, December 1987.

    Google Scholar 

  20. M. Katevenis. Fast Switching and Fair Control of Congested Flow in Broad-Band Networks. IEEE Journal on Selected Areas in Communications, SAC-5(8):1315–1326, October 1987.

    Google Scholar 

  21. M. Katevenis, D. Serpanos, and E. Spyridakis. Credit-Flow-Controlled ATM versus Wormhole Routing. Technical Report 171, ICS-FORTH, Heraklio, Crete, Greece, July 1996. URL: file://ftp.ics.forth.gr/tech-reports/1996/1996.TR171.ATM_vs_Wormhole.ps.gz.

    Google Scholar 

  22. M. Katevenis, S. Sidiropoulos, and C. Courcoubetis. Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. IEEE Journal on Selected Areas in Communications, 9(8):1265–1279, October 1991.

    Google Scholar 

  23. M. Katevenis, P. Vatsolaki, A. Efthymiou, and M. Stratakis. VC-level Flow Control and Centralized Buffering. In Proceedings of the Hot Interconnects III Symposium, August 1995. URL: file://ftp.ics.forth.gr/tech-reports/1995/ 1995.HOTI.VCflowCtrlTeleSwitch.ps.gz.

    Google Scholar 

  24. H.T. Kung, T. Blackwell, and A. Chapman. Credit-Based Flow Control for ATM Networks: Credit Update Protocol, Adaptive Credit Allocation, and Statistical Multiplexing. In Proceedings of the ACM SIGCOMM '94 Conference, pages 101–114, 1994.

    Google Scholar 

  25. R. Marbot, A. Cofler, J-C. Lebihan, and R. Nezamzadeh. Integration of Multiple Bidirectional Point-to-Point Serial Links in the Gigabits per Second Range. In Proceedings of the Hot Interconnects I Symposium, 1993.

    Google Scholar 

  26. H. Ohsaki and e.a. Rate-Based Congestion Control for ATM Networks. In Proceedings of the ACM SIGCOMM '95 Conference, pages 60–72, 1995.

    Google Scholar 

  27. J. Rinde. Routing and Control in a Centrally Directed Network. In Proc. Nat. Comput. Conf., 1977.

    Google Scholar 

  28. S. Scott and G. Thorson. The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus. In Proceedings of the Hot Interconnects IV Symposium, pages 147–156, 1996.

    Google Scholar 

  29. J. Simon and A. Danet. Controle des Ressources et Principes du Routage dans le Reseau Transpac. In Proc. Int. Symp. on Flow Control in Comp. Networks, pages 63–75, February 1979. as reported in: L. Pouzin: “Methods, Tools, and Observations on Flow Control in Packet-Switched Data Networks”, IEEE Transactions on Communications, Vol. COM-29, No. 4, April 1981, p. 422.

    Google Scholar 

  30. R. Souza, P. Krishnakumar, C. Ozveren, R. Simcoe, B. Spinney, R. Thomas, and R. Walsh. GIGAswitch System: A High-Performance Packet-Switching Platform. Digital Technical Journal, 1(6):9–22, 1994.

    Google Scholar 

  31. B. Zerrouk, V. Reibaldi, F. Potter, A. Greiner, and A. Derieux. RCube: A Gigabit Serial Links Low Latency Adaptive Router. In Proceedings of the Hot Interconnects IV Symposium, pages 13–18, 1996.

    Google Scholar 

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Dhabaleswar K. Panda Craig B. Stunkel

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© 1997 Springer-Verlag Berlin Heidelberg

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Katevenis, M.G.H., Serpanos, D., Vatsolaki, P., Markatos, E. (1997). ATLAS I: A single-chip ATM switch for NOWs. In: Panda, D.K., Stunkel, C.B. (eds) Communication and Architectural Support for Network-Based Parallel Computing. CANPC 1997. Lecture Notes in Computer Science, vol 1199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-62573-9_7

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  • DOI: https://doi.org/10.1007/3-540-62573-9_7

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-62573-5

  • Online ISBN: 978-3-540-68085-7

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