Abstract
Adaptive Logic Networks (ALNs) represent real-valued, continuous functions by means of piecewise linear approximants. ALNs have been used successfully in many applications requiring supervised learning, including control, data mining and rehabilitation. The hardware needed to train an ALN, or to evaluate the function it represents, can be quite modest, since ALN algorithms achieve high speed and efficiency by controlling the flow of execution: omitting computations involving linear pieces that are not needed for the current state change or output. Efficient flow of control can be combined with programmable hardware, as is illustrated by a field programmable gate array processor built for evaluating functions learned by ALNs.
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References
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Armstrong, W.W. (1997). Hardware requirements for fast evaluation of functions learned by Adaptive Logic Networks. In: Higuchi, T., Iwata, M., Liu, W. (eds) Evolvable Systems: From Biology to Hardware. ICES 1996. Lecture Notes in Computer Science, vol 1259. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63173-9_35
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DOI: https://doi.org/10.1007/3-540-63173-9_35
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