Parallel graph colouring using FPGAs

Abstract

In [13] a freely expandable digital architecture for feedforward neural networks was described. This architecture exploits the use of stochastic bitstreams representing real valued signals. This paper proposes a hardware implementation of a recurrent neural network to form part of a novel system for solving the graph colouring problem [5], particulary relevant to frequency assignment in mobile telecommunications systems [7].

The core elements of the design are multi-state bitstream neurons, arranged in a pipelined architecture that allow for probabilistic connections between nodes, a fixed temperature cooling schedule, and control over the degree of parallelism used in the network update rule.

We also introduce the concept of hardware paging permitting the size of graph to be unconstrained and reducing the hardware overhead.

The highly regular and compact nature of the proposed circuitry, makes it an ideal candidate for utilizing the flexibility provided by FPGA's. In such a reconfigurable system, efficient problem specific hardware is easily generated.