Abstract
FPGA based data encryption provides greater flexibility than ASICs and higher performance than software. Because FPGAs can be reprogrammed, they allow a single integrated circuit to efficiently implement multiple encryption algorithms. Furthermore, the ability to program FPGAs at runtime can be used to improve the performance through dynamic optimization. This paper describes the application of partial evaluation to an implementation of the Data Encryption Standard (DES). Each end user of a DES session shares a secret key, and this knowledge can be used to improve circuit performance. Key-specific encryption circuits require fewer resources and have shorter critical paths than the completely general design. By applying partial evaluation to DES on a Xilinx XC4000 series device we have reduced the CLB usage by 45% and improved the encryption bandwidth by 35%.
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References
B. Schneier, Applied Cryptography: Protocols, Algorithms, and Source Code in C. New York: John Wiley & Sons, 1996.
J. P. Gray and T. A. Kean, “Configurable Hardware: A New Paradigm for Computation,” presented at Decennial Cal Tech Conference on VLSI, Pasadena, CA, 1989.
M. Blaze, W. Diffie, R. L. Rivest, B. Schneier, T. Shimomura, E. Thompson, and M. Wiener, “Minimal Key Lengths for Symmetric Ciphers to Provide Adequate Commercial Security: A Report by an ad hoc Group of Cryptographers and Computer Scientists,” http://www.bsa.org/policy/eneryption/cryptographers, 1996.
I. Goldberg and D. Wagner, “Architectural Considerations for Cryptoanalytic Hardware,” http://www.cs.berkeley.edu/-iang/isaac/hardware, 1996.
S. Son, “Feasibility Study: DES Cryptanalysis Using Reconfigurable Hardware,” ftp://ftp.et.byu.edu/papers/ desfpga.ps, 1996.
W. Diffie and M. E. Hellman, “Exhaustive Cryptanalysis of the NBS Data Encryption Standard,” in IEEE Computer, vol. 10, 1977, pp. 74–84.
M. J. Wiener, “Efficient DES Key Search,” presented at CRYPTO '93, Santa Barbara, CA, 1993.
J. Villasenor, B. Schoner, K. Chia, C. Zapata, H. J. Kim, C. Jones, S. Lansing, and W. H. Mangione-Smith “Configurable Computing Solutions for Automatic Target Recognition,” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K. L. Pocek, Eds. Napa, CA, 1996, pp. 70–79.
S. Singh, J. Hogg, and D. McAuley, “Expressing Dynamic Reconfiguration by Partial Evaluation,” presented at Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, 1996.
Q. Wang and D. M. Lewis, “Automated Field-Programmable Compute Accelerator Design Using Partial Evaluation,” presented at Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, 1997.
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© 1997 Springer-Verlag Berlin Heidelberg
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Leonard, J., Mangione-Smith, W.H. (1997). A case study of partially evaluated hardware circuits: Key-specific DES. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_220
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DOI: https://doi.org/10.1007/3-540-63465-7_220
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