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Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic

  • Reconfiguration II
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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

Abstract

Dynamically reconfigurable FPGAs are increasingly being used to speed up algorithms that would previously have been executed on computers. Reconfiguration latency is the time that elapses between a request for new circuitry to be loaded onto an FPGA and the point at which the circuitry is ready for use. It is a critical parameter in the design of dynamically reconfigurable systems used for algorithm acceleration and needs to be evaluated early in the design cycle. This paper reports on the development of expert system techniques for the a priori estimation of reconfiguration latency,

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References

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Wayne Luk Peter Y. K. Cheung Manfred Glesner

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© 1997 Springer-Verlag Berlin Heidelberg

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Lysaght, P. (1997). Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_223

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  • DOI: https://doi.org/10.1007/3-540-63465-7_223

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

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