Abstract
This paper describes a reconfigurable coprocessor based on an Altera CPLD, specifically designed for a real-time computer vision system. An overview of the system is given and the architecture of the coprocessor is described, discussing the utility of its distributed memory organization for image processing applications.
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© 1997 Springer-Verlag Berlin Heidelberg
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Lisa, F., Cuadrado, F., Rexachs, D., Carrabina, J. (1997). A reconfigurable coprocessor for a PCI-based real time computer vision system. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_244
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DOI: https://doi.org/10.1007/3-540-63465-7_244
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