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A parallel algorithm for minimum cost path computation on polymorphic processor array

  • Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
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Book cover Parallel and Distributed Processing (IPPS 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1388))

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Abstract

This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh interconnection network. The proposed algorithm has been implemented using the Polymorphic Parallel C language and has been validated through simulation. The proposed algorithm for the Polymorphic Processor Array, delivers the same performance, in terms of computational complexity, as the hypercube interconnection network of the Connection Machine, and as the Gated Connection Network.

The work described in this paper has been supported by research grants from CNR (Italian Consiglio nazionale delle Ricerche) and MURST (Ministero dell'Università e della Ricerca Scientifica).

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References

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Author information

Authors and Affiliations

  1. DIST - University of Genoa, via Opera Pia 13, 16145, Genova, Italy

    P. Baglietto & M. Migliardi

  2. DEI - University of Padua, via Gradenigo, Padova, Italy

    M. Maersca

Authors
  1. P. Baglietto
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  2. M. Maersca
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  3. M. Migliardi
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José Rolim

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© 1998 Springer-Verlag Berlin Heidelberg

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Baglietto, P., Maersca, M., Migliardi, M. (1998). A parallel algorithm for minimum cost path computation on polymorphic processor array. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_666

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  • DOI: https://doi.org/10.1007/3-540-64359-1_666

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64359-3

  • Online ISBN: 978-3-540-69756-5

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