Abstract
The recent introduction of partially-reconfigurable field-programmable gate arrays (PRFPGAs) has led to the need for new algorithms suited for use with these devices. Although algorithms developed for use with field-programmable gate arrays can be applied to PRFPGAs, these algorithms do not take advantage of features available in these new devices.
This paper examines the applicability of PRFPGAs in hardware emulation systems. A partitioning algorithm known as temporal partitioning is introduced for use with PRFPGA-based hardware emulation systems.
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References
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© 1998 Springer-Verlag Berlin Heidelberg
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Spillane, J., Owen, H. (1998). Temporal partitioning for partially-reconfigurable-field-programmable gate. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_670
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DOI: https://doi.org/10.1007/3-540-64359-1_670
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