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International Parallel Processing Symposium

IPPS 1998: Parallel and Distributed Processing pp 55–60Cite as

Evaluation of a low-power reconfigurable DSP architecture

  • Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1388))

Abstract

Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.

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Author information

Authors and Affiliations

  1. Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley

    Arthur Abnous, Marlene Wan & Jan Rabaey

  2. Sony Corporation, Japan

    Katsunori Seno

  3. SHARP Corporation, Japan

    Yuji Ichikawa

Authors
  1. Arthur Abnous
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  2. Katsunori Seno
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  3. Yuji Ichikawa
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  4. Marlene Wan
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  5. Jan Rabaey
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Editor information

José Rolim

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© 1998 Springer-Verlag Berlin Heidelberg

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Cite this paper

Abnous, A., Seno, K., Ichikawa, Y., Wan, M., Rabaey, J. (1998). Evaluation of a low-power reconfigurable DSP architecture. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_673

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  • DOI: https://doi.org/10.1007/3-540-64359-1_673

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64359-3

  • Online ISBN: 978-3-540-69756-5

  • eBook Packages: Springer Book Archive

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