Abstract
Designs of delay insensitive circuits must be proven correct in two different respects. First it must be demonstrated that a design meets its functional specification. Second it must be assured that it tolerates arbitrary delays in its individual components. The latter proof requires a model explicitly mentioning wire delays, whereas the former is much easier carried out in a model neglecting such delays.
In this paper we show how explicit treatment of wire delays can be substituted by a set of implementation conditions imposed on a model neglecting wire delays. When the conditions are satisfied, the circuit is assured to be delay insensitive.
The implementation conditions are directed towards circuits consisting of self-timed elements using delay insensitive coding for data transfer.
This is a preview of subscription content, log in via an institution.
Preview
Unable to display preview. Download preview PDF.
References
Elmstrøm R., J. Frich Hansen and L. Møller Jørgensen, Systoliske algorithmer realiseret asynkront. Master's thesis [in danish], University at Århus, Computer Science Department, Ny Munkegade, DK-8000 Århus C, 1988.
Gammelgaard A., Inheriting safety properties of concurrent programs. To be published.
Greenstreet M. R., T. E. Williams and J. Staunstrup, Self-Timed Iteration. Proceedings from VLSI-87, Vancouver (editor C. Sequin), North Holland 1987.
Martin A. J., Compiling Communicating Processes into Delay-Insensitive VLSI Circuits. Distributed Computing, 1 (1986), pp. 226–234.
Miller R. E., Switching Theory, vol. 2, ch. 10. Wiley 1969.
Molnar C. E., Fang T., Rosenberger F. U., Synthesis of Delay-Insensitive Modules. Proceedings from 1985 Chapel Hill Conference on VLSI (editor H. Fuchs), pp. 67–86.
Seitz C., "System Timing". in Introduction to VLSI Systems, eds. C. Mead and L. Conway, Addison-Wesley Publishing Company 1980.
van de Snepscheut J. L. A., Trace theory and VLSI design. Lecture Notes in Computer Science 200, Springer 1985.
Staunstrup J. and M. R. Greenstreet, From High-Level Descriptions to VLSI Circuits. BIT, 28 (1988), pp. 620–638.
Toubro Nielsen E. and C. Riber Christensen, Opbygning af haendelsesstyrede kredsløb i VLSI. Master's thesis [in danish]. University at Århus, Computer Science Department, Ny Munkegade, DK-8000 Århus C, 1988.
Udding J. T., Classification and Composition of Delay-Insensitive Circuits. Doctoral Dissertation, Eindhoven University of Technology, 1984.
Udding J. T., A formal model for defining and classifying delay-insensitive circuits and systems. Distributed Computing, 1 (1986), pp. 197–204.
Verhoeff T., Delay-insensitive codes — an overview. Distributed Computing, 3 (1988), pp. 1–8.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1989 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Gammelgaard, A. (1989). Implementation conditions for delay insensitive circuits. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 365. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540512845_49
Download citation
DOI: https://doi.org/10.1007/3540512845_49
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-51284-4
Online ISBN: 978-3-540-46183-8
eBook Packages: Springer Book Archive