Definition
Switching techniques determine how messages are forwarded through the network. Specifically, these techniques determine how and when buffers and switch ports of individual routers are allocated and released and thereby the timing with which messages or message components can be forwarded to the next router on the destination path.
Discussion
Introduction
This section introduces basic switching techniques used within the routers of multiprocessor interconnection networks. Switching techniques determine when and howmessages are forwarded through the network. These techniques determine the granularity and timing with which resources such as buffers and switch ports are requested and released and consequently determine the blocking behavior of routing protocols that utilize them in different network topologies. As a result, they are key determinants of the deadlock properties of routing protocols. Further, their relationship to flow control protocols and traffic...
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Bibliography
Dally WJ (1992) Virtual-channel flow control. IEEE Trans Parallel Distrib Syst 3(2):194–205
Peh L-S, Dally WJ (2001) A delay model for router microarchitectures. IEEE Micro 21:26–34
Peh L-S, Dally WJ (2001) A delay model and speculative architecture for pipelined routers. In: Proceedings of the 7th international symposium on high-performance computer architecture, Nuevo Leone
Dally WJ, Towles B (2004) Principles and practices of interconnection networks. Morgan Kaufman, San Francisco
Choi Y, Pinkston TM (2004) Evaluation of queue designs for true fully adaptive routers. J Parallel Distrib Comput 64(5):606–616
Mullins R, West A, Moore S (2004) Low-latency virtual-channel routers for on-chip networks. In: Proceedings of the 31st annual international symposium on computer architecture, Munchen
Dally WJ, Seitz CL (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput C-36(5):547–553
Duato J, Yalamanchili S, Ni L (2003) Interconnection networks: an engineering Approach. Morgan Kaufmann, San Francisco
Flynn M (1995) Computer architecture: pipelined and parallel processor design. Jones & Bartlett, Boston, pp 63–140
Duato J et al (1996) A high performance router architecture for interconnection networks. In: Proceedings of the 1996 international conference on parallel processing, Bloomington, vol I, August 1996, pp 61–68
Scott SL, Goodman JR (1994) The impact of pipelined channels on k-ary n-cube networks. IEEE Trans Parallel Distrib Syst 5(1):2–16
Gaughan PT et al (1996) Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks. IEEE Trans Comput 45(6):651–665
Borkar S et al (1988) iWarp: an integrated solution to high-speed parallel computing. In: Proceedings of supercomputing \({}^{{\prime}}\)88, Orlando, November 1988, pp 330–339
Kermani P, Kleinrock L (1979) Virtual cut-through: a new computer communication switching technique. Comp Networks 3(4):267–286
Dally WJ, Seitz CL (1986) The torus routing chip. J Distrib Comput 1(3):187–196
Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5): 51–61
Duato J (1993) A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Syst 4(12): 1320–1331
Duato J (1995) A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Syst 6(10):1055–1067
Duato J (1996) A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans Parallel Distrib Syst 7(8):841–854
Peh L-S, Dally WJ (2000) Flit reservation flow control. In: Proceedings of the 6th international symposium on high-performance computer architecture, Toulouse, France, January 2000, pp 73–84
Stunkel CB et al (1994) Architecture and implementation of vulcan. In: Proceedings of the 8th international parallel processing symposium, Cancun, Mexico, pp 266–274
Stunkel CB et al (1994) The SP1 high-performance switch. In: Proceedings of the scalable high performance computing conference, Knoxville, pp 150–157
Seitz C (1985) The cosmic cube. Commun ACM 28(1):22–23
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Yalamanchili, S. (2011). Switching Techniques. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_296
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DOI: https://doi.org/10.1007/978-0-387-09766-4_296
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